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[操作系统]AD7190的小总结


1、单次转换模式
通过配置“模式寄存器的MD2、MD1、MD0为001”,便可启动单次转换。
流程“上电 -》 单次转换 -》 省电模式 ” , 片内振荡上电需要大约1ms。
 
单次转换的时序图:
 

数字的含义:0x08 :表示后面的数字是用来设置mode register的;
0x280060:用来设置单次转换的参数;
      0x58:读数据寄存器;
     DATA:就是ADC对应通道采集的值。
 
完成转换后,DOUT/RDY变成低电平。从数据寄存器中读取数据字后,DOUT/RDY变为高电平。如果CS为低电平,DOUT/RDY将保持高电平,直到又启动并完成一次转换为止。如果需要,即使DOUT/RDY已变为高电平,也可以多次读取数据寄存器。
 
 
2、多通道的单次转换
如果使能了多个通道,ADC将依次选择各使能通道,并在该通道上执行转换。转换启动后,DOUT/RDY变为高电平并保持该状态,直到有有效结果可用为止。转换结果一旦可用,DOUT/RDY便会变成低电平。然后ADC选择下一个通道并开始转换。在执行下一个转换过程中,用户可以读取当前的转换结果。下一转换一旦完成,数据寄存器便会更新。用户读取转换结果时间是有限的。ADC在各选择通道上均完成一次转换后,便会返回省电模式。
 
如果模式寄存器的DAT_STA位设置为1 ,则每次执行数据读取时,状态寄存器的内容将与转换结果一同输出。状态寄存器的四个LSB指示转换对应的通道。
 
3、连续转换模式
      连续转换模式是上电默认模式。
AD7190连续转换,每次转换完成时,状态机寄存器中的RDY位变为低电平。如果CS为低电平,则当一次转换完成时,DOUT/RDY将变为低电平。
若要读取转换结果,用户需要写入通信寄存器,指示下一操作为读取数据寄存器。从数据寄存器中读取数据字后,DOUT/RDY将变为高电平。如需要,用户可以多次读取该寄存器。但是,用户必须确保在下一次转换完成时,对数据寄存器的访问已经结束,否则新转换字将丢失。
 
如果使能了多个通道,ADC将连续循环选择各使能通道,每次循环均会在每个通道上执行一次转换。一旦获得转换结果,就会立即更新数据寄存器。每次转换结果可用时,DOUT/RDY将变为低电平。然后,用户可以读取转换结果,同时ADC在下一个使能通道上执行转换。
如果模式寄存器的DAT_STA位设置为1 ,则每次执行数据读取时,状态寄存器的内容将与转换结果一同输出。状态寄存器的四个LSB指示转换对应的通道。
 

 
4、连续读取
可以对AD7190记性配置,使得每次转换完成时,转换结果会自动置于DOUT/RDY线上,而无需每次写入通信寄存器以访问数据。
将0x5C(01011100)写入通信寄存器后,用户只需要提供适当的SCLK周期数,这样当转换完成时,转换字便会自动置于DOUT/RDY线路上。ADC应配置为连续转换模式。
若要退出连续读取模式,必须在RDY引脚为低电平时将指令0x58(01011000)写入通信寄存器。在连续读取模式下,ADC会监控DIN线路上的活动,以便能接收到指令以后以退出连续读取模式。
此外,如果DIN上出现40个连续1,ADC将复位。因此在连续读取模式下,DIN应保持低电平,直到有指令要写入器件。
 
如果使能了多个通道,ADC将连续依次选择各使能通道,并在所选择通道上执行一次转换。当一个转换结果可用时,DOUT/RDY便会变为低电平。当用户施加足够多的SCLK脉冲时,数据便会自动置于DOUT/RDY引脚上。
如果模式寄存器的DAT_STA位设置为1 ,则每次执行数据读取时,状态寄存器的内容将与转换结果一同输出。状态寄存器的四个LSB指示转换对应的通道。

 
类型滤波类型建立时间转换时间
禁止斩波sinc3Tsettle = 3/FadcFadc = Fclk/(1024 * FS[9:0])
sinc4Tsettle = 4/Fadc
使能斩波sinc3Tsettle = 2/FadcFadc = Fclk/(3*1024 * FS[9:0])
sinc4Fadc = Fclk/(4*1024 * FS[9:0])

 
 
 
5、P0 P1 P2 P3脚的作用
AD7190 通过外界多路复用器(如:4选1,8选1)在选择AD7190采集哪个通道。
 
 6、关于AD7190采集通道的几点问答
1、What is the sequence of events when switching between channels for the AD719x when the sequencer is disabled and continuous conversion mode is selected?
(对于AD719x来说,当序列不是使能时,并且选择了连续转换模式,如何切换通道?)
转换器开头写入通信寄存器的每个序列的事件将会指定下一个操作。
例如使用 AD7190/AD7192,通道切换操作的顺序如下是 (通道 AIN1_AIN2 和 AIN3_AIN4 )。
进行通道切换的条件是:两个通道的工作条件都是 50 赫兹输出数据速率;内部的主时钟;增益 = 1;缓冲区对双极模式;应用 REFIN1(+) 和 REFIN1(–) 之间的外部引用是 ADC 的参考源;AD719x 是 24 位部分。
每个序列的事件与此转换器开头写入通信寄存器来指定要执行下一个操作。完成指定的操作时,界面默认为等待下一个指令。
1、Write 0x8 to communications register:    This specifies that the next operation is a write to the mode register.
2、Write 0x080060 to mode register: This configures the AD719x for an output data rate of 50 Hz and the internal clock is used.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000110 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN.
5、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
6、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 24 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high.
7、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register
8、Write 0x000210 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN3–AIN4.
9、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
10、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 24 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high
11、Continually running through this loop will allow data to be read from each of the channels continuously.
 
 
 
 
2、What is the sequence of events when converting on several channels for the AD719x when the sequencer is enabled and continuous conversion mode is selected?
 
When the sequencer is enabled, the ADC automatically sequences through the enabled channels. When several channels are enabled, the bit DAT_STA in the mode register should be set to 1. When DAT_STA equals 1, the contents of the status register are output with each conversion. The LSBs of the status register indicate the channel to which the conversion corresponds.
The sequence of events using the AD7190/AD7192, for example, is as follows (Channels AIN1–AIN2 and AIN3–AIN4 being used). The operating conditions for both channels are 50 Hz output data rate, internal master clock, gain = 1, buffer on, bipolar mode; external reference applied between REFIN1(+) and REFIN1(–) is reference source for the ADC.
1、Write 0x8 to communications register: This specifies that the next operation is a write to the mode register.
2、Write 0x180060 to mode register: This configures the AD719x for an output data rate of 50 Hz; the internal clock is used and DAT_STA is set to 1.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000310 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN2 and AIN3–AIN4.
5、Continuously running the following loop allows conversions to be read back from the two channels continuously.
6、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
7、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 32 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high
 
3、What is the sequence of events when switching between channels for the AD719x when the sequencer is enabled and continuous read mode is selected?
 
When the sequencer is enabled, the ADC automatically sequences through the enabled channels. When several channels are enabled, the bit
DAT_STA in the mode register should be set to 1. When DAT_STA equals 1, the contents of the status register are output with each conversion. The LSBs of the status register indicate the channel to which the conversion corresponds. With continuous read mode enabled, the user only needs to apply the SCLK pulses when a conversion is available (RDY goes low)—  a write to the communications register for each read of the data register is not required.
The sequence of events using the AD7190/AD7192, for example, is as follows (Channels AIN1–AIN2 and AIN3–AIN4 being used). The operating conditions for both channels are 50 Hz output data rate, internal master clock, gain = 1, buffer on, bipolar mode; external reference applied between REFIN1(+) and REFIN1(–) is reference source for the ADC.
 
1、Write 0x8 to communications register: This specifies that the next operation is a write to the mode register.
2、Write 0x180060 to mode register: This configures the AD719x for an output data rate of 50 Hz, the internal clock is used and DAT_STA is set to 1.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000310 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN2 and AIN3–AIN4.
5、Write 0x5C to the communications register: This specifies that the serial interface is dedicated to continuously read the data register until this function is disabled.
6、Continuously running the following loop allows conversions to be read back from the two channels continuously.
7、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 32 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high.
8、To disable continuous read mode, the command 0x58 is written to the communications register when is low
 
 
4、If a conversion is not read and the next conversion is complete, for how long does DOUT/RDY go high?
 
The DOUT/RDY pin goes high for approximately 100 µs when the master clock is 4.9 MHz. During this time, the data register is updated with the new conversion data so the user should not attempt to read the data register.
 
5、When single conversion mode is used, can CS be taken high after the single conversion is initiated?
 
The serial interface is independent of the sampling process. So, once the single conversion is initiated, the AD719x will power up and perform the single conversion irrespective of the CS polarity. So, the user can take CS low, initiate the single conversion and then take CS high again. When the conversion is complete, CS can be taken low to read the conversion and another single conversion can be started if required.
 
When CS is taken high, the DOUT/RDY pin is tristated. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. The user can determine the end of the conversion by reading the status register. Alternatively, the conversion time could be timed out by the microcontroller clock.
 
 
6、Is the serial interface reset when CS is taken high?
 
No. CS does not reset the serial interface. To reset the serial interface, 40 1s must be written to the ADC. This will reset the on-chip registers
to their default values also.
       This architecture was used as it allows the user to read or write to the AD719x in “batches.” For example, when reading the configuration register,the contents can be read as a continuous 24-bit word or the data can be split into three 8-bit bytes. When writing to the configuration register, the information can be sent as a continuous 24-bit word; alternatively, the data can be sent as three 8-bit bytes. CS can be held low when the information is being transferred. Alternatively, CS can be used to frame each of the 8-bit bytes without affecting the data transfer process.
 
7、When information (conversion data or information from the on-chip registers) is read from the ADC, the LSB readback is always 1. Why?
The DOUT and RDY functions share a pin on the AD719x. So, the DOUT/RDY pin functions are a ready pin when CS is low. Every time a conversion is completed, the pin goes low, indicating to the microprocessor that a valid conversion is available. When the user requests a read of the data register, the DOUT/RDY pin functions are a DOUT pin. When pulses are applied to the SCLK pin, the data is placed on the DOUT pin. The data is output from the AD719x following the SCLK falling edge and is valid on the SCLK rising edge.
When the LSB of the data is placed on the DOUT/RDY pin, the DOUT/RDY pin changes its functionality so that it operates as a RDY pin. The change from the DOUT to RDY the function occurs a few nanoseconds after the SCLK rising edge. The microprocessor is latching the bits on the SCLK rising edge. So, if the microprocessor is slow, then the DOUT/RDY pin is functioning as a RDY pin when the LSB is latched into the microprocessor. So, the microprocessor reads the value of the RDY pin rather than the LSB, causing the LSB to be a 1. To prevent this, a faster microprocessor must be used.
Alternatively, general-purpose input/output pins of the microprocessor can be used to represent a serial interface. By bit-banging, the user has more control over the read instant. By reading the values on the DOUT pin when SCLK is low rather than latching in the data on the SCLK rising edge, all bits of the data read will be valid。